Main memories often use dynamic-random-access memory (DRAM), while faster cache memories and on-chip memories may use static random-access memory (SRAM). Read-only-memory (ROM) may use fuses or masked metal options, or may use electrically-erasable programmable read-only memory (EEPROM) cells. These are randomly-accessible memories since individual words can be read or written without disturbing nearby data. Often individual bytes may be written.
Mass storage memory is block-addressable, where a block of 512 or more bytes must be read or written together as a block. Individual words of 64 bytes or less cannot be separately written without re-writing the whole 512-byte block. Mass storage devices include rotating magnetic disks, optical disks, and EEPROM arranged as flash memory.
Traditionally, flash memory has been used for non-volatile storage. Another kind of non-volatile memory, phase-change memory, was discovered in the 1960's, and was even written about in a paper in Electronics magazine in September 1970 by the founder of Intel Corp., Gordon Moore. However, despite the long-felt need, this 40-year-old technology has not yet been widely used in personal computers and other systems.
Phase-change memory (PCM) uses a layer of chalcogenide glass that can be switched between a crystalline and an amorphous state. The chalcogenide glass layer can be an alloy of germanium (Ge), antimony (Sb), and tellurium (Te). This alloy has a high melting point, which produces the amorphous state when cooled from the melting point. However, when the solid alloy is heated from the amorphous state, the alloy transforms into a crystalline state at a crystallization temperature than is below its melting point. Such heating can be provided by an electric current through the alloy. The state change may occur rapidly, such as in as little as 5 nanoseconds.
One problem with phase-change memory is that write times are data-sensitive. Writing a 1 into a PCM cell may require 100 ns, while writing a 0 to a PCM cell may require only 5 or 10 ns. The cell read time may be relatively short, such as 2-10 ns. Thus writing a 1 to a cell may require 10 times longer than writing a 0 to the cell. This write asymmetry can increasing delays that can be mitigated with improved buffering and bank interleaving.
What is desired is a phase-change memory that compensates for asymmetric write times through improved buffering and caching. A phase-change memory designed for data-sensitive write delays is desired. A memory system that has the high storage density of phase-change memory yet has the rapid access time of a RAM is desirable. A page-mode phase-change memory with a page buffer and a look-up table cache for improved performance is also desirable.